JPS56152037A - Multiple controller system - Google Patents

Multiple controller system

Info

Publication number
JPS56152037A
JPS56152037A JP5457780A JP5457780A JPS56152037A JP S56152037 A JPS56152037 A JP S56152037A JP 5457780 A JP5457780 A JP 5457780A JP 5457780 A JP5457780 A JP 5457780A JP S56152037 A JPS56152037 A JP S56152037A
Authority
JP
Japan
Prior art keywords
priority
multiple controller
devices
contrast table
numbers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5457780A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6141431B2 (en]
Inventor
Makoto Hidaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5457780A priority Critical patent/JPS56152037A/ja
Publication of JPS56152037A publication Critical patent/JPS56152037A/ja
Publication of JPS6141431B2 publication Critical patent/JPS6141431B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
JP5457780A 1980-04-24 1980-04-24 Multiple controller system Granted JPS56152037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5457780A JPS56152037A (en) 1980-04-24 1980-04-24 Multiple controller system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5457780A JPS56152037A (en) 1980-04-24 1980-04-24 Multiple controller system

Publications (2)

Publication Number Publication Date
JPS56152037A true JPS56152037A (en) 1981-11-25
JPS6141431B2 JPS6141431B2 (en]) 1986-09-16

Family

ID=12974547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5457780A Granted JPS56152037A (en) 1980-04-24 1980-04-24 Multiple controller system

Country Status (1)

Country Link
JP (1) JPS56152037A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0211634U (en]) * 1988-06-30 1990-01-24

Also Published As

Publication number Publication date
JPS6141431B2 (en]) 1986-09-16

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